Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 163

Address
(offset)
0x119D6 CP timers event register (RTER)
0x119DA CP timers mask register (RTMR)
0x119DC CP time-stamp timer control register (RTSCR)
0x119DE Reserved
0x119E0 CP time-stamp register (RTSR)
0x119F0 BRG1 configuration register (BRGC1)
0x119F4 BRG2 configuration register (BRGC2)
0x119F8 BRG3 configuration register (BRGC3)
0x119FC BRG4 configuration register (BRGC4)
0x11A00 SCC1 general mode register (GSMR_L1)
0x11A04 SCC1 general mode register (GSMR_H1)
0x11A08 SCC1 protocol-specific mode register (PSMR1)
0x11A0A Reserved
0x11A0C SCC1 transmit-on-demand register (TODR1)
0x11A0E SCC1 data synchronization register (DSR1)
0x11A10 SCC1 event register (SCCE1)
0x11A14 SCC1 mask register (SCCM1)
0x11A16 Reserved
Freescale Semiconductor
Table 3-1. Internal Memory Map (continued)
Register
BRGs 1–4
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W Size
R/W 16 bits
R/W 16 bits
— 16 bits
R/W 16 bits
R/W 32 bits
R/W 32 bits
R/W 32 bits
R/W 32 bits
R/W 32 bits
SCC1
R/W 32 bits
R/W 32 bits
R/W 16 bits
— 16 bits
R/W 16 bits
R/W 16 bits
R/W 16 bits
R/W 16 bits
— 8 bits
Memory Map
Reset Section/Page
0x0000_0000 14.6.4/14-24
0x0000_0000
0x0000 14.3.8/14-11
—
0x0000 14.3.9/14-11
0x0000_0000 17.1/17-2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000 20.1.1/20-3
0x0000_0000
0x0000 20.1.2/20-9
21.16/21-12
(UART)
22.8/22-7
(HDLC)
23.11/23-10
(BISYNC)
24.9/24-8
(Transparent)
25.17/25-14
(Ethernet)
— —
0x0000 20.1.4/20-10
0x7E7E 20.1.3/20-9
0x0000 21.19/21-19
(UART)
0x0000
22.11/22-12
(HDLC)
23.14/23-15
(BISYNC)
24.12/24-11
(Transparent)
25.20/25-20
(Ethernet)
— —
3-17