Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 162

Memory Map
Address
(offset)
0x114F2 TC8 error cells counter (TC_ECC8)
0x114F4 Reserved
0x11500 TC general status register (TCGSR)
0x11502 TC general event register (TCGER)
0x115F0 BRG5 configuration register (BRGC5)
0x115F4 BRG6 configuration register (BRGC6)
0x1115F8 BRG7 configuration register (BRGC7)
0x115FC BRG8 configuration register (BRGC8)
0x11600– Reserved
0x1185F
2
0x11860 I C mode register (I2MOD)
0x11861 Reserved
2
0x11864 I C address register (I2ADD)
0x11865 Reserved
2
0x11868 I C BRG register (I2BRG)
0x11869 Reserved
2
0x1186C I C command register (I2COM)
0x1186D Reserved
2
0x11870 I C event register (I2CER)
0x11871 Reserved
2
0x11874 I C mask register (I2CMR)
0x11875– Reserved
0x119BF
0x119C0 Communications processor command register (CPCR)
0x119C4 CP configuration register (RCCR)
0x119C8– Reserved
0x119D5
3-16
Table 3-1. Internal Memory Map (continued)
Register
4
TC Layer—General
4
4
BRGs 5–8
Communications Processor
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W Size
R/W 16 bits
— 12 bytes
4
R 16 bits
R/W 16 bits
R/W 32 bits
R/W 32 bits
R/W 32 bits
R/W 32 bits
— 608
bytes
2
I C
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 315
bytes
R/W 32 bits
R/W 32 bits
— 14 bytes
Reset Section/Page
0x0000 34.4.3.3/34-12
— —
0x0000 34.4.2.2/34-11
0x0000 34.4.2.1/34-11
0x0000_0000 17.1/17-2
0x0000_0000
0x0000_0000
0x0000_0000
— —
0x00 39.4.1/39-6
— —
0x00 39.4.2/39-6
— —
0x00 39.4.3/39-7
— —
0x00 39.4.5/39-8
— —
0x00 39.4.4/39-7
— —
0x00 39.4.4/39-7
— —
0x0000_0000 14.4.1/14-13
0x0000_0000 14.3.7/14-8
— —
Freescale Semiconductor