Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 491

Bit Name
20 G5T1 General-purpose line 5 timing 1. Defines the state of GPL5 during phase 1–2.
0 The value of the GPL5 line at the rising edge of T1 will be 0
1 The value of the GPL5 line at the rising edge of T1 will be 1
21 G5T3 General-purpose line 5 timing 3. Defines the state of GPL5 during phase 3–4.
0 The value of the GPL5 line at the rising edge of T3 will be 0
1 The value of the GPL5 line at the rising edge of T3 will be 1
22–23 REDO Redo current RAM word. See
(REDO)."
00 Normal operation
01 The current RAM word is executed twice.
10 The current RAM word is executed tree times.
11 The current RAM word is executed four times.
Note: For Rev A.1 and forward: for any value other than 00, do not use REDO on two consecutive
24 LOOP Loop. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.
The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end
are defined as the loop. The number of times the UPM executes this loop is defined in the
corresponding loop field of the M x MR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
See
25 EXEN Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an
exception pattern at the exception start address (EXS) at a fixed address in the RAM array.
When the PowerQUICC II under UPM control begins accessing a memory device, the external
device may assert TEA or SRESET. An exception occurs when one of these signals is asserted by
an external device and the PowerQUICC II begins closing the memory cycle transfer. When one of
these exceptions is recognized and EXEN in the RAM word is set, the UPM branches to the special
exception start address (EXS) and begins operating as the pattern defined there specifies. See
Table 11-35.. The user should provide an exception pattern to deassert signals controlled by the
UPM in a controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent
data corruption. If EXEN = 0, exceptions are deferred and execution continues. After the UPM
branches to the exception start address, it continues reading until the LAST bit is set in the RAM
word.
0 The UPM continues executing the remaining RAM words.
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
exception condition is detected. The exception condition can be an external device asserting TEA
or SRESET.
26–27 AMX Address multiplexing. Determines the source of A[0–31] at the rising edge of t1
(single-PowerQUICC II mode only). See
00 A[0–31] is the non-multiplexed address. For example, column address.
01 Reserved.
10 A[0–31] is the address requested by the internal master multiplexed according to M x MR[AM x ].
11 A[0–31] is the contents of MAR. Used for example, during SDRAM mode initialization.
Freescale Semiconductor
Table 11-36. RAM Word Bit Settings (continued)
"Section 11.6.4.1.5, "Repeat Execution of Current RAM Word
CPM RAM words. The second word will not execute.
Section 11.6.4.1.4, "Loop
For example, row address.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Control."
Section 11.6.4.2, "Address
Memory Controller
Multiplexing."
11-73