Paragraph
Number
11.6.1.4
Exception Requests.............................................................................................. 11-67
11.6.2
Programming the UPMs .......................................................................................... 11-67
11.6.3
Clock Timing ........................................................................................................... 11-67
11.6.4
The RAM Array....................................................................................................... 11-69
11.6.4.1
RAM Words......................................................................................................... 11-70
11.6.4.1.1
11.6.4.1.2
11.6.4.1.3
11.6.4.1.4
11.6.4.1.5
11.6.4.2
Address Multiplexing .......................................................................................... 11-77
11.6.4.3
11.6.4.4
Signals Negation.................................................................................................. 11-78
11.6.4.5
The Wait Mechanism ........................................................................................... 11-78
11.6.4.6
11.6.5
11.6.6
11.7
11.7.0.1
EDO Interface Example....................................................................................... 11-92
11.8
11.8.1
11.8.2
Slow Devices Example .......................................................................................... 11-101
11.9
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
External Masters Timing........................................................................................ 11-103
11.9.5.1
12.1
L2 Cache Configurations ............................................................................................... 12-1
12.1.1
Copy-Back Mode....................................................................................................... 12-1
12.1.2
Write-Through Mode ................................................................................................. 12-2
12.1.3
ECC/Parity Mode....................................................................................................... 12-4
12.2
12.3
12.4
L2 Cache Operation ....................................................................................................... 12-7
12.5
Timing Example............................................................................................................. 12-7
xviii
Contents
Loop Control.................................................................................................... 11-76
Secondary (L2) Cache Support
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Chapter 12
Page
Number
Freescale Semiconductor