Paragraph
Number
2.5.1
PowerPC Exception Model........................................................................................ 2-21
2.5.2
2.5.3
Exception Priorities.................................................................................................... 2-25
2.6
Memory Management.................................................................................................... 2-25
2.6.1
PowerPC MMU Model.............................................................................................. 2-25
2.6.2
2.7
Instruction Timing.......................................................................................................... 2-27
2.8
Differences between the PowerQUICC II's G2 Core and the
MPC603e Microprocessor ......................................................................................... 2-28
4.1
System Configuration and Protection .............................................................................. 4-2
4.1.1
Bus Monitor ................................................................................................................. 4-3
4.1.2
Timers Clock................................................................................................................ 4-3
4.1.3
Time Counter (TMCNT).............................................................................................. 4-4
4.1.4
4.1.5
Software Watchdog Timer ........................................................................................... 4-6
4.2
Interrupt Controller .......................................................................................................... 4-7
4.2.1
Interrupt Configuration ................................................................................................ 4-8
4.2.1.1
Machine Check Interrupt ......................................................................................... 4-9
4.2.1.2
INT Interrupt............................................................................................................ 4-9
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.4.1
4.3
Programming Model ...................................................................................................... 4-17
4.3.1
4.3.1.1
SIU Interrupt Configuration Register (SICR)........................................................ 4-17
4.3.1.2
SIU Interrupt Priority Register (SIPRR)................................................................ 4-18
4.3.1.3
4.3.1.4
4.3.1.5
4.3.1.6
SIU Interrupt Vector Register (SIVEC) ................................................................. 4-24
Freescale Semiconductor
Contents
Chapter 3
Memory Map
Chapter 4
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
vii