Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 923

– Sequence number generation
– Sequence number protection (CRC-3 and even parity) generation
— Structured AAL1 cell format
– Automatic synchronization using the structured pointer during reassembly
– Structured pointer generation during segmentation
— Unstructured AAL1 cell format
– Clock recovery using external SRTS (synchronous residual time stamp) logic during
reassembly
– SRTS generation using external logic during segmentation
• AAL0 format
— Receive
– Whole cell is put in memory
– CRC10 pass/fail indication
— Transmit
– Reads a whole cell from memory
– CRC10 insertion option
• AAL1 circuit emulation service (refer to
more information)
• AAL2 format
— Refer to Chapter 32, "ATM AAL2"
• Support for user-defined cells
— Support cells up to 65 bytes
— Extra header insert/load on a per-frame basis
— Extra header size has byte resolution
— Asymmetric cell size for send and receive
— HEC octet insertion option
• PHY
— UTOPIA level II supports 8/16 bits 25/50 MHz
– Supports UTOPIA master and slave modes
– Supports cell-level handshake
– Supports multiple-PHY polling mode
• ATM pace control (APC) unit
— Peak cell rate pacing on a per-VC basis
— Peak-and-sustain cell rate pacing using GCRA on a per-VC basis
— Peak-and-minimum cell rate pacing on a per-VC basis
— Up to eight priority levels
— Fully managed by CP with no host intervention
• Available bit rate (ABR)
Freescale Semiconductor
Chapter 31, "ATM AAL1 Circuit Emulation Service,"
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
ATM Controller and AAL0, AAL1, and AAL5
for
30-3