Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 158

Memory Map
Address
(offset)
0x1133C FCC2 transmit internal rate registers for PHY0
(FTIRR2_PHY0)
0x1133D FCC2 transmit internal rate registers for PHY1
(FTIRR2_PHY1)
0x11133E FCC2 transmit internal rate registers for PHY2
(FTIRR2_PHY2)
0x1133F FCC2 transmit internal rate registers for PHY3
(FTIRR2_PHY3)
0x11340 FCC3 general mode register (GFMR3)
0x11344 FCC3 protocol-specific mode register (FPSMR3)
0x11348 FCC3 transmit on-demand register (FTODR3)
0x1134A Reserved
0x1134C FCC3 data synchronization register (FDSR3)
0x1134E Reserved
0x11350 FCC3 event register (FCCE3)
0x11352 Reserved
0x11354 FCC3 mask register (FCCM3)
0x11356 Reserved
0x11358 FCC3 status register (FCCS3)
0x11359– Reserved
0x113FF
3-12
Table 3-1. Internal Memory Map (continued)
Register
3
3
3
3
3
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W Size
R/W 8 bits
R/W 8 bits
R/W 8 bits
R/W 8 bits
3
FCC3
R/W 32 bits
3
R/W 32 bits
3
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R 16 bits
— 167
bytes
Reset Section/Page
0x00 30.13.4/30-91
(ATM)
33.4.2.1.2/33-26
0x00
(IMA)
0x00
0x00
0x0000_0000 29.2/29-3
0x0000_0000 30.13.2/30-88
(ATM)
33.4.2.1.1/33-26
(IMA)
35.18.1/35-18
(Ethernet)
36.6/36-7
(HDLC)
0x0000 29.5/29-8
— —
0x7E7E 29.4/29-8
— —
0x0000_0000 30.13.3/30-90
(ATM)
35.18.2/35-20
(Ethernet)
36.9/36-14
(HDLC)
— —
0x0000_0000 30.13.3/30-90
(ATM)
35.18.2/35-20
(Ethernet)
36.9/36-14
(HDLC)
— —
0x00 36.10/36-16
(HDLC)
— —
Freescale Semiconductor