Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 854

Multi-Channel Controllers (MCCs)
1
Offset Name
0x00 TSTATE
0x04 ZISTATE
0x08 ZIDATA0
0x0C ZIDATA1
0x10 TBDFlags Hword TxDB flags, used by the CP (read-only for the user)
0x12 TBDCNT
0x14 TBDPTR
0x18 INTMSK
0x1A CHAMR
0x1C TCRC
0x20 RSTATE
0x24 ZDSTATE
0x28 ZDDATA0
0x2C ZDDATA1
0x30 RBDFlags Hword RxBD flags, used by the CP (read-only for the user)
0x32 RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
0x34 RBDPTR
28-6
Table 28-2. Channel-Specific Parameters for HDLC
Width
Word Tx internal state. To start a transmitter channel the user must write to TSTATE
0xHH80_0000. HH is the TSTATE high byte described in
Transmitter State (TSTATE)—HDLC
Word Zero-insertion machine state. User-initialized to one of the following values:
0x10000207 for regular channel transmitting all 1s before first frame of data
0x00000207 for regular channel transmitting flags before first frame of data
0x30000207 for inverted channel transmitting all 1s before first frame of data
0x20000207 for inverted channel transmitting flags before first frame of data
Note: Used in conjunction with ZIDATA0 and ZIDATA1.
Word Zero-insertion high word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA1.
Word Zero-insertion low word data buffer. User-initialized to one of the following values:
0xFFFFFFFF allows transmission of all 1s before first frame of data
0x7E7E7E7E allows transmission of flags before first frame of data
Note: Used in conjunction with ZISTATE and ZIDATA0.
Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
Word Tx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
Hword Channel's interrupt mask flag. See
and Interrupt Mask (INTMSK)—AAL1
Hword Channel mode register. See
(CHAMR)—HDLC
Word Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only
for the user)
Word Rx internal state. To start a receiver channel the user must write to RSTATE
0xHH80_0000. HH is the RSTATE high byte described in
Receiver State (RSTATE)—HDLC
Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and
0x20FFFFE0 for inverted channel)
Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
for the user)
Word Rx internal data pointer. Points to current absolute data address of channel, used by
the CP (read-only for the user)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Mode."
Section 28.3.3.1.1, "Interrupt Circular Table Entry
CES."
Section 28.3.1.3, "Channel Mode Register
Mode."
Mode."
Section 28.3.1.1, "Internal
Section 28.3.1.4, "Internal
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