Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 284

The 60x Bus
60x Bus Specification
1
TT[0–4]
Command Transaction
00000 Clean block Address
00100 Flush block Address
01000 sync
01100 Kill block
10000 eieio
101 00 Graphics
write
11000 TLB
invalidate
11100 Graphics
read
00001 lwarx
reservation
set
00101 Reserved
01001 tlbsync
01101 icbi
8-10
Table 8-2. Transfer Type Encoding
2
PowerQUICC II as Bus Master
Bus Trans.
Address only
only (if enabled)
Address only
only (if enabled)
Address Address only
only (if enabled)
Address Address only
only
Address Address only
only (if enabled)
Single-beat Single-beat
write write
(non-GLB)
Address Not applicable Not applicable
only
Single-beat Single-beat
read read
(non-GBL)
Address Not applicable Not applicable
only
— Not applicable Not applicable
Address Not applicable Not applicable
only
Address Not applicable Not applicable
only
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
PowerQUICC I
I as Snooper
Transaction Source Action on Hit
dcbst (if enabled) Not applicable
dcbf (if enabled) Not applicable
sync (if enabled) Not applicable
dcbz or dcbi (if Flush, cancel
enabled) reservation
eieio (if enabled) Not applicable
ecowx Not applicable
Not applicable
eciwx Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
PowerQUICC II
as Slave
Action on Slave Hit
AACK asserted;
PowerQUICC II takes
no further action.
AACK is asserted;
PowerQUICC II takes
no further action.
Assert AACK. BG is
negated until
PowerQUICC II
buffers are flushed.
AACK is asserted.
Assert AACK. BG is
negated until
PowerQUICC II
buffers are flushed.
No action.
AACK is asserted;
PowerQUICC II takes
no further action.
PowerQUICC II takes
no action.
Address-only
operation. AACK is
asserted;
PowerQUICC II takes
no further action.
Illegal
Address-only
operation. AACK is
asserted;
PowerQUICC II takes
no further action.
Address-only
operation. AACK is
asserted;
PowerQUICC II takes
no further action.
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