Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 237

Part III
The Hardware Interface
Intended Audience
Part III is intended for system designers who need to understand how each PowerQUICC II signal works
and how those signals interact.
Contents
Part III describes external signals, clocking, memory control, and power management of the
PowerQUICC II.
It contains the following chapters:
• Chapter 6, "External Signals,"
PowerQUICC II signals.
• Chapter 7, "60x Signals,"
• Chapter 8, "The 60x Bus,"
• Chapter 10, "Clocks and Power Control,"
PowerQUICC II.
• Chapter 9, "PCI Bridge,"
bridge PCI agents to a host processor that implements the PowerPC architecture and how it is
compliant with PCI Specification Revision 2.2.
• Chapter 11, "Memory Controller,"
of eight memory banks shared between a general-purpose chip-select machine (GPCM) and three
user-programmable machines (UPMs).
• Chapter 12, "Secondary (L2) Cache Support,"
configuration of a level-2 cache.
• Chapter 13, "IEEE 1149.1 Test Access Port,"
port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
Freescale Semiconductor
shows a functional pinout of the PowerQUICC II and describes the
describes signals on the 60x bus.
describes the operation of the bus used by PowerPC processors.
describes how the PCI bridge enables the PowerQUICC II to gluelessly
describes the memory controller, which controlling a maximum
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
describes the clocking architecture of the
provides information about implementation and
describes the dedicated user-accessible test access
III-1