Paragraph
Number
11.4
SDRAM Machine ........................................................................................................ 11-33
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
Bank Interleaving .................................................................................................... 11-37
11.4.5.1
11.4.5.2
11.4.6
11.4.6.1
11.4.6.2
11.4.6.3
Column Address to First Data Out-CAS Latency............................................. 11-40
11.4.6.4
11.4.6.5
Last Data In to Precharge-Write Recovery ....................................................... 11-41
11.4.6.6
11.4.6.7
11.4.6.8
11.4.7
SDRAM Interface Timing ....................................................................................... 11-43
11.4.8
11.4.9
SDRAM Mode-Set Command Timing .................................................................... 11-47
11.4.10
SDRAM Refresh...................................................................................................... 11-47
11.4.11
SDRAM Refresh Timing ......................................................................................... 11-48
11.4.12
11.4.12.1
11.4.13
11.5
General-Purpose Chip-Select Machine (GPCM)......................................................... 11-51
11.5.1
Timing Configuration .............................................................................................. 11-53
11.5.1.1
11.5.1.2
11.5.1.3
Relaxed Timing.................................................................................................... 11-56
11.5.1.4
11.5.1.5
11.5.1.6
Extended Hold Time on Read Accesses .............................................................. 11-59
11.5.2
External Access Termination ................................................................................... 11-61
11.5.3
Boot Chip-Select Operation..................................................................................... 11-62
11.5.4
11.6
11.6.1
Requests ................................................................................................................... 11-64
11.6.1.1
Memory Access Requests.................................................................................... 11-66
11.6.1.2
11.6.1.3
Software Requests-run Command .................................................................... 11-67
Freescale Semiconductor
Contents
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
xvii