Paragraph
Number
8.2.2
60x-Compatible Bus Mode.......................................................................................... 8-3
8.3
8.3.1
Arbitration Phase ......................................................................................................... 8-5
8.3.2
Address Pipelining and Split-Bus Transactions........................................................... 8-6
8.4
8.4.1
Address Arbitration...................................................................................................... 8-7
8.4.2
Address Pipelining....................................................................................................... 8-8
8.4.3
8.4.3.1
8.4.3.2
8.4.3.3
8.4.3.4
8.4.3.5
8.4.3.6
8.4.3.7
8.4.3.8
Extended Transfer Mode ....................................................................................... 8-19
8.4.4
8.4.4.1
8.4.4.2
8.4.5
Pipeline Control ......................................................................................................... 8-24
8.5
Data Tenure Operations ................................................................................................. 8-25
8.5.1
Data Bus Arbitration.................................................................................................. 8-25
8.5.2
Data Streaming Mode ................................................................................................ 8-26
8.5.3
8.5.4
8.5.5
8.5.6
8.6
Memory Coherency-MEI Protocol ............................................................................. 8-30
8.7
Processor State Signals .................................................................................................. 8-31
8.7.1
8.7.2
TLBISYNC Input ...................................................................................................... 8-32
8.8
Little-Endian Mode........................................................................................................ 8-32
9.1
Signals.............................................................................................................................. 9-3
9.2
Clocking........................................................................................................................... 9-3
9.3
PCI Bridge Initialization .................................................................................................. 9-3
9.4
SDMA Interface............................................................................................................... 9-3
9.5
Freescale Semiconductor
Contents
Chapter 9
PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
xi