Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 529

In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the following
restrictions:
• All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed must use either
ECC (BRx[DECC] = 0b11) or read-modify-write parity (BRx[DECC] = 0b10). See
Section 11.3.1, "Base Registers (BRx),"
register parameters.
• Only PowerQUICC II-type masters are supported in systems that use ECC/parity L2 cache mode.
See Section 11.9, "External Master Support (60x-Compatible Mode),"
external master types.
Figure 12-3. shows a PowerQUICC II connected to an MPC2605 integrated L2 cache in ECC/Parity
mode.
Freescale Semiconductor
for more information about the PowerQUICC II base
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Secondary (L2) Cache Support
for more information about
12-5