Table of Contents
Advertisement
TECHNICAL DESCRIPTION
by pin 33 of the LCA. Scratch pad and data RAM are provided internally by
the MCU. A programmable logic cell array, (LCA) U10 contains address
decoding and glue logic for various peripherals on the board.
An onboard oscillator, also part of the LCA, is crystal controlled. Its' 9.216
MHz frequency (test point T7) is used in conjunction with phase locked
loop U15 to generate a microprocessor clock frequency of 11.50849 MHz
which is available on the µCLK test point. This frequency is internally
divided by 12 in the MCU, resulting in a processor operating frequency of
approximately 960 KHz.
VIDEO IN
EV-COM
Inter-module
serial comm.
Figure 6-10: 615 Module Block Diagram
6.5.2
Adjusting the LTC Output Level
The time code out for the LTC translator/phase restorer is generated
internally by the LCA, and is available on pin test point LTCO. U18 shapes
the square wave to the correct rise and fall times. Buffer U19 is a low
impedance driver to give a balanced time code output. The output level of
the LTC generator is set at the factory to 0 dbm into a 600 ohm load, but
may be adjusted using VR3.
6.5.3
Sync Separator (6150-31)
Composite video, buffered on the separate I/O module, and on the main
PCB by Q5 and Q4, is AC coupled into the sync separator U8. The sync
separator provides H Sync, V Sync, a Frame pulse (active low for field 1)
and a back porch clamp pulse to drive the DC restorer circuitry U16 and
associated components.
compare the actual DC level of the video to ground potential. If they are
not equal, U16 generates an error signal that adjusts the bias point of Q5
thus ensuring proper operation of the video keyer with varying video and
sync levels. Comparator U7 switches when the negative sync tip goes
Model 4025TR Film Footage Encoder Manual
LTC OUT
I/O
LTC GENERATOR
VITC GENERATOR
The back porch clamp pulse allows U16 to
VIDEO OUT + VITC
FORMATING SWITCHES
Page 6-14
Advertisement
Table of Contents
