Table of Contents
Advertisement
!
6.8 VITC GENERATOR AND CHARACTER GENERATOR CIRCUIT DESCRIPTION
TECHNICAL DESCRIPTION
6.7.3 Character Generator Interface
The character inserter logic and keyer are contained on a separate circuit
sub-module (6231) which connects to the main circuit card via header J4 &
J5. Video in and out, and the MCU address and data bus are fed up the
header from the main board.
The submodule used for the 632 Character generator is identical to the VITC
generator submodule. Jumper JP3 at the front of the sub-module selects the
VITC mode when it is in the HI position and the Character mode when it is in
the LO position. See section 6.8 for the circuit description that applies to
both the VITC and Character generator uses of this board.
The 6231 video keyer submodule is used for both the VITC generator and
for the character generator in the 4025TR. This submodule can be used
with either the 6150 or 6120 base processor boards, as needed. Video in
and out, and the MCU address and data bus are fed up the header from
the main board.
generator functions is contained in a programmable logic device (LCA) U7.
Its program is loaded from EPROM U8 on power up. Jumper JP3, located
at the front of the board determines whether the VITC generator
configuration or the character generator configuration will be loaded. The
VITC generator configuration also has the ability to display some
rudimentary characters, although this is not its primary function.
6.8.1
VITC Generator Logic (6231-32) & (6231-33)
On earlier versions of the 6231, the VITC bit rate for PAL and NTSC are
generated by two crystal-controlled oscillators consisting of XT1 and U14a
(for PAL) and XT2 and U14b (for NTSC), and associated components. The
NTSC/PAL control signal (NP test point) controls which crystal oscillator is
active.
Jumper JP8 controls whether the VITC oscillator or character
oscillator is present on the DCLK test point. Set JP8 to the V position to
measure the VITC frequency. The oscillator output is buffered by U14c
and may be measured at the DCLK test point when jumper JP8 is in the V
position.
Jumper JP9 controls whether the PAL or NTSC oscillator is
active. Set JP9 to the P position to measure the PAL oscillator, position N
to measure the NTSC oscillator. Both JP8 and JP9 should be set to the A
position for normal operation. The frequency of 14.31818 MHz for NTSC,
or 14.5 MHz for PAL is 8 times the VITC bit rate. The VITC oscillator is
divided by 8 in the LCA to generate the correct VITC bit rate.
On later versions of the board, the VITC bit rate is generated a crystal-
controlled oscillator consisting of XT1 and U14a and associated
components. On these version of the board XT2 will not be installed.
Jumper JP8 controls whether the VITC oscillator or character oscillator is
present on the DCLK test point. Set JP8 to the V position to measure the
Model 4025TR Film Footage Encoder Manual
The majority of the logic for the VITC and character
Page 6-21
Advertisement
Table of Contents
