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Model 4025 Film Footage Encoder Manual
which is available on the µCLK test point. This frequency is internally
divided by 12 in the MCU, resulting in a processor operating frequency of
approximately 960 KHz.
VIDEO IN
LTC OUT
VIDEO OUT + VITC
I/O
EV-COM
LTC GENERATOR
FORMATING SWITCHES
Inter-module
serial comm.
VITC GENERATOR
Figure 6-10: 615 Module Block Diagram
6.5.2. Adjusting the LTC Output Level
The time code out for the LTC translator/phase restorer is generated
internally by the LCA, and is available on pin test point LTCO. U18 shapes
the square wave to the correct rise and fall times. Buffer U19 is a low
impedance driver to give a balanced time code output. The output level of
the LTC generator is set at the factory to 0 dbm into a 600 ohm load, but
may be adjusted using VR3.
6.5.3. Sync Separator (6150-31)
Composite video, buffered on the separate I/O module, and on the main
PCB by Q5 and Q4, is AC coupled into the sync separator U8. The sync
separator provides H Sync, V Sync, a Frame pulse (active low for field 1)
and a back porch clamp pulse to drive the DC restorer circuitry U16 and
associated components.
The back porch clamp pulse
allows U16 to
compare the actual DC level of the video to ground potential. If they are
not equal, U16 generates an error signal which adjusts the bias point of Q5
thus ensuring proper operation of the video keyer with varying video and
sync levels. Comparator U7 switches when the negative sync tip goes
below its half amplitude point, producing a stable sync called PRECN-
SYNC.
6.5.4. Colour Frame Detector (6150-31)
Monostable U1a is triggered by the leading edge of PRECN-SYNC and
times out about 6 µsec later. U1b is triggered by the trailing edge of U1a,
generating a burst sample window CBWINDOW (available at test point
TECHNICAL DESCRIPTION
Page 6-16
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