Character Generator Logic (6231-32) - evertz 4025TR Instruction Manual

Model 4025TR Film Footage Encoder Manual
VITC frequency. The oscillator output is buffered by U14c and may be
measured at the DCLK test point when jumper JP8 is in the V position. JP8
should be set to the A position for normal operation. The frequency of
14.425 MHz is 8 times the VITC bit rate. The VITC oscillator is divided by
8 in the LCA to generate the correct VITC bit rate.
The starting position of the VITC on the line is fixed internally in the LCA
such that the first bit of code is approximately 10.5 µsec (11.5 µsec for
PAL) after the leading edge of horizontal sync.
Once per field, the MCU loads the VITC bit pattern for a particular line into
static RAM U9. It is thus possible for the 4025TR to generate different
VITC data for individual video lines. In practice, the 4025TR will generate
one line pair for the primary VITC generator and another for the secondary
line pair. On lines where VITC is enabled, the LCA accesses the static
RAM and fetches the VITC data one byte (8 bits) at a time. The VITC sync
bits and cyclic redundancy check byte (CRC) are generated internally in
the LCA and inserted into the VITC bit stream in the appropriate place.
The VITC data is clocked out of the LCA on the KEYFILL output (U7 pin 7)
and into buffer U8a. The VITC keyer is controlled by the KEY signal
generated in the LCA (U7 pin 6). The data is clocked out of the LCA with
the VITC clock, so that the bit width is not dependent on propagation
delays in the LCA. VITC bits are shaped by U6b and associated
components, and presented to the video keyer when the VITC/CHAR
signal is LOW.
6.8.2

Character Generator Logic (6231-32)

The character display is formatted to display 28 (32 for PAL) rows of 32
characters each in the tiny size, 14 (16 for PAL) rows the small size, and 7
(8 for PAL) rows in the large size. Each of the character positions
corresponds to one location in static RAM U9. The MCU writes characters
into specified locations in the RAM corresponding to the position of the
characters on the screen. RAM locations are scanned during each
television field. Valid characters address corresponding sections of the
character PROM U8 and are loaded into the LCA one byte (8 bits) at a
time. Each byte corresponds to either the left or right half of a character
pixel line. The internal logic in the LCA control how many lines per
character and how many character lines there are on the raster, according
to registers set by the firmware.
The character data is clocked out of the LCA on the KEYFILL output (U7
pin 7). A special character with all bits set to 1 is written into all positions of
the RAM where no characters are to be displayed. These characters
disable the keyer by the KEY signal, generated in the LCA (U7 pin 6).
When other characters are present the KEY signal becomes active,
allowing the characters to be keyed into the video signal. The character
data is clocked out of the LCA with the dot clock, so that the pixel width is
not dependent on propagation delays in the LCA. The pixels are presented
to the video keyer when the VITC/CHAR signal is HIGH. A control register
in the LCA selects whether the characters will be white or black, and
TECHNICAL DESCRIPTION Page 6-22