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6.7 VIDEO CHARACTER INSERTER CIRCUIT DESCRIPTION
TECHNICAL DESCRIPTION
6.6.4
High Speed VITC Reader (6111-30)
The clock and data separator circuitry for the VITC reader is contained on a
separate sub-module that connects to the main circuit card via header J1.
Composite video, VSYNC, and some control signals from the MCU are fed
up the header from the main circuit board.
Composite video is buffered and DC restored by Q2, U14 and associated
components, to provide REF VIDEO to comparator U15, which recovers
VITC data from the DC restored video. U16 and associated components
provide a reference level to U15, of approximately one half the peak VITC
level, to ensure proper extraction of the VITC data regardless of the video
level.
At VSYNC, the MCU releases the reset to U7b, enabling the VITC reader
circuitry. The first VITC data bit turns on U7a, which releases the reset to
CRC detector U1 and U3. A phase locked loop consisting of VCO U13,
and U12, U17, and U18, provides an 8 times bit rate clock to divider U11,
which generates a series of timing pulses at the VITC bit rate (1.78977
MHz for NTSC, 1.8125 MHz for PAL). Each positive going transition of the
VITC data re-synchronizes the divider so that the VITC recovery clock at
U5 pin 13 occurs in the middle of each bit.
Inverted VITC data is shifted into U3 that calculates the cyclic redundancy
check (CRC) word for the recovered data. Valid CRC and 90 bits of code,
detected by U1, clocks U7b on, disabling the VITC clock and generating a
VITC RDY signal to the MCU. The MCU unloads the VITC data through
switch U17, located on the main circuit board.
The 632 character generator is a microcontroller based module functionally
divided into the following hardware subsystems:
1. Microcontroller & I/O
2. Sync Separator/Video processing
3. Character Generator logic
4. Character Generator Keyer
Model 4025TR Film Footage Encoder Manual
Page 6-19
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