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Architecture
In the device, there are two LUTs in the PAT. Each LUT can map up to 128MB of objects at a 4KB page
granularity. The four modes share the two LUTs .
One of the recommended usages, as shown in
modes and the other LUT for paged mode accesses. With this scheme up to 128MB of objects can be
available simultaneously in 8,16 and 32-bit modes and another 128MB of objects for paged mode
accesses.
Figure 2-24. Using LUT to Translate Tiled Virtual Address to Physical SDRC Address
Tiler virtual
address space
Increasing
addresses
NOTE: You need to ensure that an object allocated in a particular container mode does not
physically overlap with any other object either in the same mode or other container modes.
2.2.2.6
Page Definition
A TILER page defines the granularity of object allocation in virtual TILER containers. Given that the
sub-page structure is mode specific, the 4KB page is the smallest granularity common to all modes,
making it the granularity to consider in the TILER resource manager for object allocation.
2.2.2.6.1 Container Geometry with 4-kiB Pages
As pages size is 4KB, any 128MB object container is a set of 256x128 = 32768 pages, organized in an
array of 256 columns and 128 rows, as shown in
P
0,0
P
0,1
P
0,2
P
0,3
P
P
0,4
y
356
DMM/TILER
Preliminary
8-bit mode container
16-bit mode container
32-bit mode container
Page mode container
Figure 2-25. Object Container Geometry with 4KB Pages
P
P
P
P
1,0
2,0
3,0
4,0
P
P
P
P
1,1
2,1
3,1
4,1
P
P
P
P
1,2
2,2
3,2
4,2
P
P
P
P
1,3
2,3
251,126
252,126
P
P
P
249,127
250,127
251,127
252,127
© 2011, Texas Instruments Incorporated
Figure
2-24, is - to use one LUT for 8,16, and 32-bit
LUT 0
LUT 1
PAT page-grained
physical address
translation LUT
Increasing
addresses
Figure
2-25.
P
P
P
5,0
6,0
255,123
P
P
P
5,1
254,124
255,124
P
P
P
253,125
254,125
255,125
P
P
P
253,126
254,126
255,126
P
P
P
253,127
254,127
255,127
www.ti.com
SDRAM physical
address space
physically translated by
x
P
4-kiB page
x,y
Increasing
addresses
SPRUGX9 – 15 April 2011
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