Fig. 6.7.32 Rom Correction Enable Register - Renesas 7200 Series User Manual

APPENDIX
6.7 Control registers
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Fig. 6.7.31 Interrupt control register 2
ROM correction enable register
b7 b6 b5 b4 b3 b2 b1 b0

Fig. 6.7.32 ROM correction enable register

6-50
0
Interrupt control register 2 (ICON2) [Address 00FF
B Name
0 INT1 interrupt
enable bit (IT1E)
1 INT2 interrupt enable
bit (IT2E)
2 Serial I/O interrupt
enable bit (S1E)
3 Fix this bit to "0."
4 f(X )/4096 interrupt
IN
enable bit (MSE)
5
Fix these bits to "0."
to
7
0
0
ROM correction enable register (RCR) [Address 0212
B
Block 1 enable bit (RCR0) 0 : Disabled
0
Block 2 enable bit (RCR1)
1
Fix these bits to "0."
2, 3
4
Nothing is assigned. These bits are write disable bits.
to When these bits are read out, the values are "0."
7
7220 Group User's Manual
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Name
1 : Enabled
0 : Disabled
1 : Enabled
]
16
After reset R W
0 R W
0 R W
0 R W
0 R W
0 R W
0 R W
Address 00FF
]
16
Functions After reset R W
0
0
0
0
Address 0212
16
16