Fig. 2.8.5 Connection Port Control By Bsel0 And Bsel1 - Renesas 7200 Series User Manual

2
(4) I C Control Register (S1D: address 00DA
2
The I C control register (address 00DA
Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt
request signal occurs immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become "000
transmitted and received in 8 bits.
Bit 3: I 2 C-BUS interface use enable bit (ESO)
This bit enables usage of the multi-master I
disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set
to "1," use of the interface is enabled.
When ESO = "0," the following is performed.
• PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I
00F8 ).
16
• Writing data to the I
Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the
addressing format is selected, so that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or when a general call (refer to "(5)
2
I C Status Register," bit 1) is received, transmission processing can be performed. When this bit
is set to "1," the free data format is selected, so that slave addresses are not recognized.
Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing
format is selected. In this case, only the high-order 7 bits (slave address) of the I
register (address 00D8
addressing format is selected, all the bits of the I
data.
Bit 6 and 7: Connection control bits between I
This bits controls the connection between SCL and ports or SDA and ports. When using the ports
as multi-master I
(output mode).
Figure 2.8.5 shows the connection port control by BSEL0 and BSEL1, Figure 2.8.6 shows the I
control register.
) controls the data communication format.
16
2
C data shift register (address 00D7
) are compared with address data. When this bit is set to "1," the 10-bit
16
2
C-BUS interface, set the corresponding bits of port P1 direction register to "1"
7220 Group User's Manual
FUNCTIONAL DESCRIPTION
2.8 Multi-master I
)
16
2
C-BUS interface. When this bit is set to "0," the use
) is disabled.
16
2 C address register are compared with address
2 C-BUS interface and ports (BSEL0, BSEL1)
SCL
Multi-master
2
I C-BUS
interface
SDA

Fig. 2.8.5 Connection port control by BSEL0 and BSEL1

2 C-BUS interface
" and the address data is always
2
2
C status register at address
"0"
"1" BSEL0
"0"
"1" BSEL1
"0"
"1" BSEL0
"0"
"1" BSEL1
2
C address
2
C
SCL1/P1
1
SCL2/P1
2
SDA1/P1
3
SDA2/P1
4
2-53