Fig. 4.5.4 Memory Map Of Sfr (Special Function Register) (2) - Renesas 7200 Series User Manual

SFR Area (addresses E0
Register
Address
E0 Horizontal position register (HR)
16
E1 Vertical position register 1 (CV1)
16
E2 Vertical position register 2 (CV2)
16
E3
16
E4
Character size register (CS)
16
E5 Border selection register (MD)
16
E6 Color register 0 (CO0)
16
E7
Color register 1 (CO1)
16
E8 Color register 2 (CO2)
16
E9 Color register 3 (CO3)
16
EA CRT control register (CC)
16
EB
16
EC
CRT port control register (CRTP)
16
ED CRT clock selection register (CK)
16
EE
A-D control register 1 (AD1)
16
EF A-D control register 2 (AD2)
16
F0
Timer 1 (TM1)
16
F1
Timer 2 (TM2)
16
F2
Timer 3 (TM3)
16
F3
Timer 4 (TM4)
16
F4
Timer 12 mode register (T12M)
16
F5 Timer 34 mode register (T34M)
16
F6
PWM5 register (PWM5)
16
F7
16
F8
16
F9
Interrupt input polarity register (RE)
16
FA
Test register (TEST)
16
FB CPU mode register (CPUM)
16
FC Interrupt request register 1 (IREQ1)
16
FD Interrupt request register 2 (IREQ2)
16
FE Interrupt control register 1 (ICON1)
16
FF Interrupt control register 2 (ICON2)
16

Fig. 4.5.4 Memory map of SFR (special function register) (2)

to FF )
16 16
Bit allocation
< >
:
Function bit
:
Name
:
No function bit
: Fix this bit to "0"
0
(do not write "1")
1 : Fix this bit to "1"
(do not write "0")
Bit allocation
b7
HR5 HR4 HR3
CV16 CV15 CV14 CV13
CV26 CV25 CV24 CV23
CS21
CO05 CO03
CO15 CO13
CO25 CO23
CO35 CO33
OP7 OP6 OP5 OUT
0 0 0 0 0
ADM4
ADC5 ADC4 ADC3
0
T12M4 T12M3
T34M5 T34M4 T34M3
0
RE5 RE4 RE3 CK0
00
16
1 1 1 1 1
IT3R VSCR CRTR TM4R
0
MSR CK0
IT3E VSCE CRTE TM4E
0 0 0 0
MSE
7220 Group User's Manual
M37220M3-XXXSP/FP
4.5 Functional description
State immediately after reset
<
: "0" immediately after reset
0
: "1" immediately after reset
1
: Undefined immediately
?
after reset
State immediately after reset
b0 b7
HR2 HR1 HR0
0
CV12 CV11 CV10
? ?
0
CV22 CV21 CV20
? ?
0 0 0
CS20 CS11 CS10
0 0 0
MD20 MD10
CO02 CO01
CO12 CO11
CO22 CO21
CO32 CO31
CC2 CC1 CC0
R/G/B VSYC HSYC
0
CK1 CK0
0 0 0
ADM2 ADM1 ADM0
ADC2 ADC1 ADC0
T12M2 T12M1 T12M0
T34M2 T34M1 T34M0
0 0 0 0 0
CM2
0 0 1 1 1
TM3R TM2R TM1R
S1R 1T2R 1T1R
TM3E TM2E TM1E
1T2E 1T1E
S1E
>
b0
00
16
? ? ? ? ?
? ? ? ? ?
?
0
? ? ? ?
0 0 ? 0 ?
00
16
00
16
00
16
00
16
00
16
?
00
16
00
16
0 0 0 0
?
00
16
FF
16
07
16
FF
16
07
16
00
16
00
16
?
?
?
0 0 0 0 ?
00
16
1 1 1 0 0
00
16
00
16
00
16
00
16
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