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APPLICATION
5.4 Example of I
2
(2) Read processing routine
Slave address
S
(W) "A0
Initialization
S2 (address 00DB
S1D (address 00DA
IICE (bit6 at address 00FE
S1 (address 00D9
S1 (address 00D9
(A)←Slave address (R) "A1
TRX (bit 6 at address 00D9
ACK BIT (bit 6 at address 00DB
ACK BIT (bit 6 at address 00DB
S0 (address 00D7
No (not end)
Note 2: The timeout count is performed by software with interrupts, such as timers. Accordingly, if receive
operation is not completed due to various influences, the loop continues. Therefore, if receive
operation does not complete within a certain time, I C-BUS access is stopped by outputting STOP
condition. If I
Fig. 5.4.5 Flowchart of read processing routine
5-24
C-BUS interface control (M37221Mx-XXXSP/FP)
A
A
C
Sub-address
C
"
16
K
K
Read start
←"11000101
)
16
)
←"01001000
16
←"0"
)
16
←"00010000
)
16
(A)←Slave address (W) "A0
16
Data output
) ← "00100000
"
16
2
"
16
Data output
←"0"
)
16
←"0"
)
16
Immediately before
the last receive byte?
Yes
)←"1"
16
)←"FF
"
16
16
Preparation for judging of timeout.
Timeout ? (See note 2)
No
Waiting receive end
PIN (bit 4 at address 00D9
)≠"1"?
16
Yes (end)
Store recive data to internal RAM
2
C-BUS access is stopped by timeout, the obtained data is incorrect data.
7220 Group User's Manual
A
Slave address
R
C
Data
(R) "A1
"
S
16
K
"
2
"
2
2
Disable multi-master I
"
Setting for outputting the START condition
2
in data output processing routine.
"
Transmit the START condition, slave
address (W) , and sub-address.
Transmit the RESTART condtion and
slave address (R).
Set to receive mode
Set ACK return mode.
No
Set to non-ACK return mode.
No
Input start
(Set dummy data to
generate clock.)
Yes
I
S1 (address 00F8
S1 (address 00F8
I
2
A:
Accumulator
2
S0:
I
C data shift register
2
S1:
I
C status register
A
2
S2:
I
C clock control register
C
P
2
S1D:
I
C control register
K
IICE:
Multi-master I
interrupt enable bit
BB:
Bus busy flag
TRX:
Communication mode
specification bit
ACK BIT:
ACK bit
2
PIN:
I
C-BUS interface interrupt
request bit
RS:
Restart condition
C-BUS interface.
End of reception of
the last receive byte
Yes
After data is received, no
acknowledge bits are
generated, but the STOP
condition is sent by the
master, completing this
read operation.
←"1"
←"11000000
)
"
16
2
)
←"11010000
16
"
2
←"0"
Transmit the STOP condition.
Note 1: Be sure to set between S1
and S1 within 10 machine cycles.
End
2
C interface
Within 10
machine
cycles
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