Construction Of Multi-Master I; Bus Interface; Fig. 2.8.1 Block Diagram Of Multi-Masteer I - Renesas 7200 Series User Manual

FUNCTIONAL DESCRIPTION
2.8 Multi-master I
Serial
Noise
data elimination
(SDA)
circuit
Noise
Serial
elimination
clock
circuit
(SCL)

Fig. 2.8.1 Block diagram of multi-masteer I

2.8.1 Construction of multi-master I

2
The multi-master I C-BUS interface consists of the following :
2
I C address register
I 2 C data shift register
I 2 C clock control register
2
I C control register
2
I C status register
Other control circuits
The data transfer with the internal CPU is performed via data bus, the data transfer with an external device
is performed via ports P1
assigned to the following functions.
P1 : Multi-master I
1
P1 : Multi-master I
2
P1 : Multi-master I
3
P1 : Multi-master I
4
The shift clock to determine the transfer speed of serial data is selected by the I
(refer to "Figure 2.8.4").
A serial data and a serial clock is referred as "SDA," "SCL" respectively, hereafter.
2-48
2 C-BUS interface
2
I C address register
b7
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
S0D
Address comparator
Data
b7
control
circuit
I C data shift register
S0
AL
circuit
BB
circuit
Clock
b7
control
ACK
FAST
circuit
ACK
MODE CCR4 CCR3 CCR2 CCR1 CCR0
BIT
S2
2
I C clock control register
2 C-BUS interface
–P1 When using multi-master I
1 4.
2 C-BUS interface Synchronous clock input/output pin 1 (SCL1)
2 C-BUS interface Synchronous clock input/output pin 2 (SCL2)
2
C-BUS interface data input/output pin 1 (SDA1)
2
C-BUS interface data input/output pin 2 (SDA2)
7220 Group User's Manual
b0
b0
2
Internal data bus
b0
System clock
Clock division
2
C-BUS interface
2 C-BUS interface, these ports P1
Interrupt Interrupt
generating request signal
circuit (IICIRQ)
b7
AL AAS AD0 LRB
MST TRX BB PIN
S1
2
I C status
register
b7
10BIT
ESO BC2 BC1 BC0
BSEL1 BSEL0 ALS
SAD
2
S1D I C control register
( φ )
Bit counter
2
C clock control register
b0
b0
–P1 are
1 4