Fig. 6.7.3 Port P5 Direction Register; Fig. 6.7.4 Port P3 Output Mode Control Register - Renesas 7200 Series User Manual

Port P5 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0

Fig. 6.7.3 Port P5 direction register

Port P3 output mode control register
b7 b6 b5 b4 b3 b2 b1 b0

Fig. 6.7.4 Port P3 output mode control register

Port P5 direction register (D5) [Address 00CB
B Name
0, 1 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are "0."
2 Port P5 direction register
to
5
6, 7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are "0."
0 0
Port P3 output mode control register (P3S) [address 00CD
B Name
0 P3 output structure
0
selection bit (P30S)
1 P3 output structure
1
selection bit (P31S)
2, 3 Fix thes bits to "0."
4 Nothing is assigned. These bits are write disable bits.
to When these bits are read out, the values are "0."
7
Note: M37220M3-XXXSP/FP
2 DA1 output enable bit
3 DA2 output enable bit
7220 Group User's Manual
6.7 Control registers
]
16
Functions After reset R W
0 : CRT output (R)
1 : Output port P5
2
0 : CRT output (G)
1 : Output port P5
3
0 : CRT output (B)
1 : Output port P5
4
0 : CRT output (OUT1)
1 : Output port P5
5
]
16
Functions After reset R W
0 : CMOS output
1 : N-channel open-drain output
0 : CMOS output
1 : N-channel open-drain output
0 : P3 input/output
0
1 : DA1 output
0 : P3 input/output
1
1 : DA2 output
APPENDIX
0 R —
0 R W
0 R W
0 R W
0 R W
0 R —
Address 00CB
16
0 R W
0 R W
0 R W
(See note)
0 R —
0 R W
0 R W
Address 00CD
16
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