Fig. 5.1.9 Timing When All Interrupt Request Bits Are "1" At The Same Sampling Point - Renesas 7200 Series User Manual

Mitsubishi 8-bit single-chip microcomputer
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APPLICATION
5.1 Example of multi-line display
(2) When setting multiple interrupts
Various priority processings are executed by enabling multiple interrupts and by setting priorities by
software. For example, to set the priority listed below;
Timer 1 interrupt
V
interrupt
SYNC
CRT interrupt
execute the following process:
Set only interrupt enable bits (ICON1, ICON2) whose priorities are higher than the current interrupt,
and enable the interrupt disable flag (I) in only the current interrupt processing routine.
Figure 5.1.9 shows the timing when all interrupt request bits (CRT, V
same sampling point.
Note: When setting multiple interrupts, be sure to determine priority levels to prevent occurrence of
plural interrupts with the same priority level.
CRT interrupt request bit
V
interrupt request bit
SYNC
Timer 1 interrupt request bit
CRT interrupt processing
V
interrupt processing
SYNC
Timer 1 interrupt processing
Interrupt disable flag (I)

Fig. 5.1.9 Timing when all interrupt request bits are "1" at the same sampling point

5-10
1
0
1
0
1
0
3
A
2
A'
7220 Group User's Manual
(series of
)
3
(series of
)
2
B'
1
, Timer 1) are "1" at the
SYNC
(series of
)
3
B
1'

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