Renesas 7200 Series User Manual page 15

Fig. 6.4.1 Wiring for RESET input pin ...................................................................................... 6-11
Fig. 6.4.2 Wiring for clock I/O pin ............................................................................................. 6-11
Fig. 6.4.3 Wiring for CNV
Fig. 6.4.4 Wiring for V
Fig. 6.4.5 Bypass capacitor across V
Fig. 6.4.6 Analog signal line and resistor and capacitor ....................................................... 6-13
Fig. 6.4.7 Wiring for large current signal line .......................................................................... 6-14
Fig. 6.4.8 Wiring for signal line where potential levels charge frequently ........................... 6-14
Fig. 6.4.9 V pattern on underside of an oscillator ............................................................... 6-14
SS
Fig. 6.4.10 Setup for I/O ports .................................................................................................. 6-15
Fig. 6.4.11 Watchidog timer by software .................................................................................. 6-16
Fig. 6.5.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............ 6-17
Fig. 6.5.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP .................. 6-18
Fig. 6.5.3 Memory assignment of M37220M3-XXXSP/FP ...................................................... 6-19
Fig. 6.6.1 SFR assignment (including internal state immediately after reset and
access characteristics) (1) (M37221Mx-XXXSP/FP) .............................................. 6-20
Fig. 6.6.2 SFR assignment (including internal state immediately after reset and
access characteristics) (2) (M37221Mx-XXXSP/FP) .............................................. 6-22
Fig. 6.6.3 Memory map of 2 page register (including internal state immediately
after reset and access characteristics) (3)
(only M37221M8-XXXSP and M37221MA-XXXSP) ............................................... 6-24
Fig. 6.6.4 SFR assignment (including internal state immediately
after reset and access characteristics) (4) (M37220M3-XXXSP/FP) .................. 6-26
Fig. 6.6.5 SFR assignment (including internal state immediately
after reset and access characteristics) (5) (M37220M3-XXXSP/FP) .................. 6-28
Fig. 6.7.1 Port Pi direction register ........................................................................................... 6-30
Fig. 6.7.2 Port P3 direction register .......................................................................................... 6-30
Fig. 6.7.3 Port P5 direction register .......................................................................................... 6-31
Fig. 6.7.4 Port P3 output mode control register ...................................................................... 6-31
Fig. 6.7.5 PWM output control register 1 ................................................................................. 6-32
Fig. 6.7.6 PWM output control register 2 ................................................................................. 6-32
Fig. 6.7.7 I 2 C data shift register ................................................................................................ 6-33
Fig. 6.7.8 I 2 C address register ................................................................................................... 6-33
2
Fig. 6.7.9 I C status register ...................................................................................................... 6-34
2
Fig. 6.7.10 I C control register ................................................................................................... 6-35
2
Fig. 6.7.11 I C clock contorol register ...................................................................................... 6-36
Fig. 6.7.12 Serial I/O mode register ......................................................................................... 6-37
Fig. 6.7.13 DA conversion register n (only M37220M3-XXXSP/FP) ..................................... 6-38
Fig. 6.7.14 Horizontal position register ..................................................................................... 6-38
Fig. 6.7.15 Vertical position register n ...................................................................................... 6-39
Fig. 6.7.16 Character size register ............................................................................................ 6-39
Fig. 6.7.17 Border selection register ......................................................................................... 6-40
Fig. 6.7.18 Color register n ........................................................................................................ 6-41
Fig. 6.7.19 CRT control register ................................................................................................ 6-42
Fig. 6.7.20 CRT port control register ........................................................................................ 6-43
Fig. 6.7.21 CRT clock selection register .................................................................................. 6-44
Fig. 6.7.22 CRT A-D control register 1 .................................................................................... 6-45
Fig. 6.7.23 A-D control register 2 ............................................................................................. 6-45
Fig. 6.7.24 Timer 12 mode register .......................................................................................... 6-46
Fig. 6.7.25 Timer 34 mode register .......................................................................................... 6-47
Fig. 6.7.26 Interrupt input polarity register ............................................................................... 6-47
Fig. 6.7.27 CPU mode register .................................................................................................. 6-48
pin ................................................................................................. 6-12
SS
pin of One Time PROM and EPROM version .............................. 6-12
PP
line and V
SS
7220 Group User's Manual
line ...................................................... 6-13
CC
after reset and access
after reset and access
List of figures
access
access
after reset and
ix