Renesas 7200 Series User Manual page 13

Fig. 2.15.1 Timing diagram at reset .......................................................................................... 2-95
Fig. 2.15.2 Internal state immediately after reset (1) ............................................................. 2-96
Fig. 2.15.3 Internal state immediately after reset (2) ............................................................. 2-97
Fig. 2.15.4 Internal state immediately after reset (3) (only M37221M8/MA-XXXSP) ........ 2-98
Fig. 2.15.5 Voltage at poweron reset ....................................................................................... 2-99
Fig. 2.15.6 Example of reset circuit (1) .................................................................................... 2-99
Fig. 2.15.7 Example of reset circuit (2) .................................................................................... 2-99
Fig. 2.16.1 Clock generating circuit block diagram ............................................................... 2-100
Fig. 2.17.1 Clock oscillation circuit using a ceramic resonator ........................................... 2-101
Fig. 2.17.2 External clock input circuit example .................................................................... 2-101
Fig. 2.17.3 Clock oscillation circuit for CRT display ............................................................. 2-101
CHAPTER 3. ELECTRICAL CHARACTERISTICS
Fig. 3.1.1 Definition diagram of timing on multi-master I
CHAPTER 4. M37220M3-XXXSP/FP
Fig. 4.2.1 Pin configuration (top view) (1) ................................................................................. 4-4
Fig. 4.2.2 Pin configuration (top view) (2) ................................................................................. 4-5
Fig. 4.4.1 Functional block diagram ............................................................................................ 4-8
Fig. 4.5.1 Access area ................................................................................................................ 4-10
Fig. 4.5.2 Memory assignment ................................................................................................... 4-11
Fig. 4.5.3 Memory map of SFR (special function register) (1) ............................................. 4-12
Fig. 4.5.4 Memory map of SFR (special function register) (2) ............................................. 4-13
Fig. 4.5.5 Interrupt request register 1 (address 00FC
Fig. 4.5.6 Interrupt control register 1 (address 00FE
Fig. 4.5.7 D-A converter block diagram .................................................................................... 4-17
Fig. 4.5.8 DA n conversion register (addresses 00DE
Fig. 4.5.9 Port P3 output mode control register (address 00CD
Fig. 4.5.10 CRT display circuit block diagram ......................................................................... 4-20
Fig. 4.5.11 Example of display character data storing form .................................................. 4-21
Fig. 4.5.12 Structure of CRT display RAM .............................................................................. 4-23
Fig. 4.5.13 Border selection register (addresses 00E5
Fig. 4.5.14 Color register n (addresses 00E6
Fig. 4.5.15 CRT control register (address 00EA
Fig. 4.5.16 CRT port control register (address 00EC
Fig. 4.5.17 Internal state immediately after reset (1) ............................................................. 4-26
Fig. 4.5.18 Internal state immediately after reset (2) ............................................................. 4-27
CHAPTER 5. APPLICATION
Fig. 5.1.1 Connection example .................................................................................................... 5-2
Fig. 5.1.2 Display example ........................................................................................................... 5-2
Fig. 5.1.3 Flowchart of initialization processing routine ........................................................... 5-3
Fig. 5.1.4 Flowchart of V
Fig. 5.1.5 Flowchart of CRT interrupt processing routine ........................................................ 5-5
Fig. 5.1.6 Set of display character data ..................................................................................... 5-6
Fig. 5.1.7 Example of setup timing for line counter and display character data .................. 5-7
Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts ..................... 5-9
Fig. 5.1.9 Timing when all interrupt request bits are "1" at the same sampling point ..... 5-10
16
interrupt processing routine ....................................................... 5-4
SYNC
7220 Group User's Manual
2
C-BUS ............................................ 3-5
) ........................................................ 4-16
16
) ......................................................... 4-16
16
and 00DF ) .................................. 4-18
16 16
) ...................................... 4-18
16
) ...................................................... 4-24
16
to 00E9 ) .................................................... 4-24
16
) ................................................................. 4-25
16
) ......................................................... 4-25
16
List of figures
vii