Table of Contents
Advertisement
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 6.7.7 I
2
C data shift register
2
I
C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
2
Fig. 6.7.8 I
C address register
2
I C data shift register (S0) [Address 00D7
B
Name
0
D0 to D7
This is an 8-bit shift register to store
to
receive data and write transmit data.
7
2
Note:
To write data into the I C data shift register after setting the MST bit to
"0" (slave mode), keep an interval of 8 machine cycles or more.
2
I
C address register (S0D) [Address 00D8
B
Name
0
Read/write bit
(RBW)
1
Slave address
to
(SAD0 to SAD6)
7
7220 Group User's Manual
6.7 Control registers
]
16
Functions
After reset
Indeterminate
]
16
Functions
0: Read
1: Write
The address data transmitted from
the master is compared with the
contents of these bits.
APPENDIX
R W
R W
Address 00D7
16
After reset R W
R W
0
R W
0
Address 00D8
16
6-33
Advertisement
Table of Contents
