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APPENDIX
6.7 Control registers
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Fig. 6.7.27 CPU mode register
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 6.7.28 Interrupt request register 1
6-48
1
1
1
0
0
CPU mode register (CPUM) (CM) [Address 00FB
B
Fix these bits to "0."
0, 1
Stack page selection
2
bit (CM2)
3
Fix these bits to "1."
to
5
6, 7
Note: This bit is set to "1" after reset release.
Interrupt request register 1 (IREQ1) [Address 00FC
B
0
Timer 1 interrupt
request bit
1 Timer 2 interrupt
request bit
2 Timer 3 interrupt
request bit
3 Timer 4 interrupt
request bit
4 CRT interrupt
request bit
5 V
SYNC
request bit
Multi-master I
6
interrupt request bit
7
INT3 interrupt
request bit
: "0" can be set by software, but "1" cannot be set.
Note : M37220M3-XXXSP/FP
Nothing is assigned. This bit is a write disable bit.
6
When this bit is read out, the value is "0."
7220 Group User's Manual
Name
Functions
0: 0 page
1: 1 page
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
(TM1R)
0 : No interrupt request issued
(TM2R)
1 : Interrupt request issued
0 : No interrupt request issued
(TM3R)
1 : Interrupt request issued
0 : No interrupt request issued
(TM4R)
1 : Interrupt request issued
0 : No interrupt request issued
(CRTR)
1 : Interrupt request issued
interrupt
0 : No interrupt request issued
(VSCR)
1 : Interrupt request issued
2
C-BUS interface
0 : No interrupt request issued
(IICR)
1 : Interrupt request issued
0 : No interrupt request issued
(IT3R)
1 : Interrupt request issued
]
16
After reset
R W
0
R W
(Note)
1
R W
1
R W
Indeterminate
R W
Address 00FB
]
16
After reset R W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Address 00FC
16
(See note)
—
16
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