Renesas 7200 Series User Manual page 11

CHAPTER 1. OVERVIEW
Fig. 1.2.1 Pin configuration (top view) (1) ................................................................................. 1-5
Fig. 1.2.2 Pin configuration (top view) (2) ................................................................................. 1-6
Fig. 1.4.1 Functional block diagram ............................................................................................ 1-9
CHAPTER 2. FUNCTIONAL DESCRIPTION
Fig. 2.1.1 Registers configuration diagram ................................................................................ 2-2
Fig. 2.1.2 CPU mode register ...................................................................................................... 2-3
Fig. 2.1.3 Sequence of push onto/pop from a stack during interrupts and
subroutine calls ............................................................................................................ 2-5
Fig. 2.1.4 Contents of stack after execution of BRK instruction ............................................. 2-7
Fig. 2.2.1 Access area of M37221M4-XXXSP and M37221M6-XXXSP/FP ........................... 2-8
Fig. 2.2.2 Access area of M37221M8-XXXSP and M37221MA-XXXSP ................................. 2-9
Fig. 2.3.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............ 2-11
Fig. 2.3.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP .................. 2-12
Fig. 2.3.3 Memory map of SFR (special function register) (1) ............................................. 2-13
Fig. 2.3.4 Memory map of SFR (special function register) (2) ............................................. 2-14
Fig. 2.3.5 Memory map of 2 page register (only M37221M8-XXXSP and
M37221MA-XXXSP) ................................................................................................... 2-15
Fig. 2.3.6 I/O setting example of port ...................................................................................... 2-16
Fig. 2.3.7 Access to timer registers .......................................................................................... 2-18
Fig. 2.4.1 I/O pin block diagram (1) ......................................................................................... 2-24
Fig. 2.4.2 I/O pin block diagram (2) ......................................................................................... 2-25
Fig. 2.5.1 V interrupt generation timing .............................................................................. 2-27
SYNC
Fig. 2.5.2 Interrupt control logic ................................................................................................ 2-29
Fig. 2.5.3 Interrupt request register 1 (address 00FC
Fig. 2.5.4 Interrupt request register 2 (address 00FD
Fig. 2.5.5 Interrupt control register 1 (address 00FE
Fig. 2.5.6 Interrupt control register 2 (address 00FF
Fig. 2.5.7 Interrupt input polatiry register (address 00F9
Fig. 2.5.8 CRT port control register (address 00EC
Fig. 2.5.9 Interrupt control system ............................................................................................ 2-33
Fig. 2.5.10 Interrupt vector table ............................................................................................... 2-33
Fig. 2.6.1 Timer 1, timer 2, timer 3, and timer 4 block diagram .......................................... 2-34
Fig. 2.6.2 Timer overflow timing ................................................................................................ 2-35
Fig. 2.6.3 Timer 12 mode register (address 00F4
Fig. 2.6.4 Timer 34 mode register (address 00F5
Fig. 2.6.5 Example of timer system .......................................................................................... 2-38
Fig. 2.7.1 Serial I/O block diagram ........................................................................................... 2-41
Fig. 2.7.2 Serial I/O mode register (address 00DC
Fig. 2.7.3 Serial input/output common transfer mode block diagram ................................... 2-42
Fig. 2.7.4 Serial I/O register when receiving (when SM5 = "0") ........................................... 2-43
Fig. 2.7.5 Serial I/O register when transmitting (when SM5 = "0") ...................................... 2-44
Fig. 2.7.6 Timing diagram of serial I/O .................................................................................... 2-45
Fig. 2.7.7 Connection example for serial I/O transmit/receive .............................................. 2-46
Fig. 2.7.8 Serial data transmit/receive processing sequence ................................................ 2-46
List of figures
7220 Group User's Manual
) ........................................................ 2-30
16
) ........................................................ 2-30
16
) ......................................................... 2-31
16
).......................................................... 2-31
16
) ................................................... 2-32
16
) ........................................................... 2-32
16
) .............................................................. 2-36
16
) .............................................................. 2-37
16
) ............................................................ 2-41
16
List of figures
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