Fig. 2.4.1 I/O Pin Block Diagram (1) - Renesas 7200 Series User Manual

FUNCTIONAL DESCRIPTION
2.4 Input/Output pins
P0 /PWM0–P0 /PWM5, P3
0 5
N-channel open-drain output
P1 /OUT2, P1 /SCL1, P1
0 1
P2 /S , P2 /S , P2
0 CLK 1 OUT
CMOS output
Notes 1 :
When ports P1
serial I/O output pins, their output structure is N-channel open-drain output.
2 :
For the output structure of ports P3
(In the case of N-channel open-drain output, the block diagram is the same as below).
P0 /INT2/A-D4, P0 /INT1
6 7
N-channel open-drain output
indicates a pin.

Fig. 2.4.1 I/O pin block diagram (1)

2-24
2
Data bus
/SCL2, P1 /SDA1, P1
2 3
/S , P2 /TIM3, P2 /TIM2, P2
2 IN 3 4
Data bus
–P1 are used as multi-master I C-BUS interface pin and when ports P2
1 4
, P3 , either CMOS output or N-channel open-drain output is selected
0 1
Data bus
7220 Group User's Manual
Direction register
Port latch
/SDA2, P1 /A-D1/INT3, P1
4 5
–P2 , P3 /A-D5, P3
5 7 0
Direction register
Port latch
2
Direction register
Port latch
/A-D2, P1 /A-D3,
6 7
/A-D6
1
, P2 are used as
0 1