Xilinx VC707 User Manual page 29

System Clock (SYSCLK_P and SYSCLK_N)
[Figure
The VC707 board has a LVDS 200 MHz oscillator (U51) soldered onto the back side of the
board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is
named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins E19 and E18
respectively.
•
•
•
For more details, see the SiTime SiT9102 data sheet
shown in
X-Ref Target - Figure 1-9
Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N)
[Figure
The VC707 board has a programmable low-jitter 3.3V differential oscillator (U34)
connected to the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and
USER_CLOCK_N clock signal pair are connected to FPGA U1 pins AK34 and AL34
respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to
810 MHz through an I
its default frequency of 156.250 MHz.
•
•
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
1-2, callout 7]
Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential Output
Figure 1-9.
C30
0.1 μF 10V
X5R
GND
Figure 1-9: System Clock Source
1-2, callout 8]
2
C interface. Power cycling the VC707 board reverts the user clock to
Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)
Differential Output
www.xilinx.com
[Ref 18]. The system clock circuit is
VCC2V5
U51
SIT9102
200 MHz
Oscillator
1 6
OE VCC
2 5
NC OUT_B
3 4
GND OUT
Feature Descriptions
SYSCLK_N
R166
100Ω 1%
SYSCLK_P
UG885_c1_09_020612
29
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