Xilinx VC707 User Manual page 102

For the virtex-7 fpga
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Appendix C: Master Constraints File Listing
102
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#UART
set_property PACKAGE_PIN AU36 [get_ports USB_UART_RX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN AU33 [get_ports USB_UART_TX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN AT32 [get_ports USB_UART_RTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN AR34 [get_ports USB_UART_CTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
#LCD
set_property PACKAGE_PIN AN41 [get_ports LCD_RS_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_RS_LS]
set_property PACKAGE_PIN AT40 [get_ports LCD_E_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_E_LS]
set_property PACKAGE_PIN AR42 [get_ports LCD_RW_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_RW_LS]
set_property PACKAGE_PIN AT42 [get_ports LCD_DB4_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB4_LS]
set_property PACKAGE_PIN AR38 [get_ports LCD_DB5_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB5_LS]
set_property PACKAGE_PIN AR39 [get_ports LCD_DB6_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB6_LS]
set_property PACKAGE_PIN AN40 [get_ports LCD_DB7_LS]
set_property IOSTANDARD LVCMOS18 [get_ports LCD_DB7_LS]
#ROTARY
set_property PACKAGE_PIN AW31 [get_ports ROTARY_PUSH]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_PUSH]
set_property PACKAGE_PIN AR33 [get_ports ROTARY_INCA]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_INCA]
set_property PACKAGE_PIN AT31 [get_ports ROTARY_INCB]
set_property IOSTANDARD LVCMOS18 [get_ports ROTARY_INCB]
#LED
set_property PACKAGE_PIN AM39 [get_ports GPIO_LED_0_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_0_LS]
set_property PACKAGE_PIN AN39 [get_ports GPIO_LED_1_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_1_LS]
set_property PACKAGE_PIN AR37 [get_ports GPIO_LED_2_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_2_LS]
set_property PACKAGE_PIN AT37 [get_ports GPIO_LED_3_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_3_LS]
set_property PACKAGE_PIN AR35 [get_ports GPIO_LED_4_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_4_LS]
set_property PACKAGE_PIN AP41 [get_ports GPIO_LED_5_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_5_LS]
set_property PACKAGE_PIN AP42 [get_ports GPIO_LED_6_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_6_LS]
set_property PACKAGE_PIN AU39 [get_ports GPIO_LED_7_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_7_LS]
#SMA
set_property PACKAGE_PIN AN31 [get_ports USER_SMA_GPIO_P]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_P]
set_property PACKAGE_PIN AP31 [get_ports USER_SMA_GPIO_N]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_N]
set_property PACKAGE_PIN AJ32 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_CLOCK_P]
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VC707 Evaluation Board
UG885 (v1.4) May 12, 2014

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