Xilinx VC707 User Manual page 30

Chapter 1: VC707 Evaluation Board Features
For more details, see the Silicon Labs Si570 data sheet
shown in
X-Ref Target - Figure 1-10
Note:
User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N)
[Figure
An external high-precision clock signal can be provided to the FPGA bank 14 by
connecting differential clock signals through the onboard 50Ω SMA connectors J31 (P) and
J32 (N). The differential clock signal names are USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N, which are connected to FPGA U1 pins AJ32 and AK32
respectively. The user-provided 1.8 V differential clock circuit is shown in
X-Ref Target - Figure 1-11
30
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Figure 1-10.
VCC3V3
R15
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U52)
GND
Figure 1-10: User Clock Source
Figure 1-10
In , USER_CLOCK_N and USER_CLOCK_P are differential clock signals.
1-2, callout 9]
SMA
Connector
SMA
Connector
Figure 1-11: User SMA Clock Source
www.xilinx.com
[Ref 19]. The user clock circuit is
U34
Si570
Programmable
Oscillator
1 6
NC VDD
2
OE
7
5 USER CLOCK N
SDA
CLK-
8
4 USER CLOCK P
SCL CLK+
3
GND
J31
USER_SMA_CLOCK_P
J32 GND
USER_SMA_CLOCK_N
GND
UG885_c1_11_020612
VCC3V3
C192
0.01 μF 25V
X7R
GND
10 MHz - 810 MHz
50 PPM
UG885_c1_10_021412
Figure 1-11.
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014