Xilinx VC707 User Manual page 38

Chapter 1: VC707 Evaluation Board Features
Table 1-14: GTX Quad 114 PCIe Edge Connector Connections (Cont'd)
Quad 114
Pin Name
MGTXRXP1_114_AF4
MGTXRXN1_114_AF3
MGTXTXP2_114_AH4
MGTXTXN2_114_AH3
MGTXRXP2_114_AE6
MGTXRXN2_114_AE5
MGTXTXP3_114_AG2
MGTXTXN3_114_AG1
MGTXRXP3_114_AD4
MGTXRXN3_114_AD3
MGTREFCLK0P_114_AD8
MGTREFCLK0N_114_AD7
MGTREFCLK1P_114_AF8
MGTREFCLK1N_114_AF7
For more information refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
[Ref 6]
Suite (PG054)
38
Send Feedback
FPGA (U1)
Net Name
Pin
AF4 PCIE_RX6_P
AF3 PCIE_RX6_N
AH4 PCIE_TX5_P
AH3 PCIE_TX5_N
AE6 PCIE_RX5_P
AE5 PCIE_RX5_N
AG2 PCIE_TX4_P
AG1 PCIE_TX4_N
AD4 PCIE_RX4_P
AD3 PCIE_RX4_N
AD8 SI5324_OUT_C_P
AD7 SI5324_OUT_C_N
AF8 NC
AF7 NC
and 7 Series FPGAs Integrated Block for PCI Express Product Guide for Vivado Design
[Ref 7].
www.xilinx.com
PCIe Edge Connector (P1)
PCIe Edge
Pin
Pin Name
B41 PETp6
B42 PETn6
A39 PERp5
A40 PERn5
B37 PETp5
B38 PETn5
A35 PERp4
A36 PERn4
B33 PETp4
B34 PETn4
U24.28
through C32
U24.29
through C31
FHG1761
Placement
GTXE2_CHANNEL_X1Y5
GTXE2_CHANNEL_X1Y5
GTXE2_CHANNEL_X1Y6
GTXE2_CHANNEL_X1Y6
GTXE2_CHANNEL_X1Y6
GTXE2_CHANNEL_X1Y6
GTXE2_CHANNEL_X1Y7
GTXE2_CHANNEL_X1Y7
GTXE2_CHANNEL_X1Y7
GTXE2_CHANNEL_X1Y7
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014