Xilinx VC707 User Manual page 78

Chapter 1: VC707 Evaluation Board Features
over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous
read rate of 80 MHz.
X-Ref Target - Figure 1-37
U3
P28F00AG18FE
1Gb Flash Memory
RST_B
CLK
WE_B
OE_B
ADV_B
NC
A27
A[26:01]
D[15:00]
CE_B
RDWR_B
(VCC, VCCQ, 1.8V)
78
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SW9
Part of
GND
SW11
Mode
Switch
1.8V
Part of
SW11
A25
A24
GND
FLASH_A[25:0]
U40
Oscillator
80 MHz
Figure 1-37: VC707 Board Configuration Circuit
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U1
FPGA
PROG_B
VBATT
TCK
TMS
Bank 0
TDI
(VCCO = 1.8V)
TDO
M[2:0]
INIT_B
DONE
CCLK
FWE_B
FOE_B
ADV_B
RS1
RS0
Bank 15
(VCCO = 1.8V)
NC
A[26:25]
A[23:16]
A[15:00]
D[15:00]
Bank 14
(VCCO = 1.8V)
FCS_B
WAIT
EMCCLK
VCCAUXIO (2.0V)
D6
BAS40-04
5 kΩ
1.8V
B1
261Ω
GND
3.3V
DS10
GREEN
261Ω
Q15
NDS331N
460 mW
GND
UG885_c1_34_030512
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014