Gtx Transceivers - Xilinx VC707 User Manual

Chapter 1: VC707 Evaluation Board Features
X-Ref Target - Figure 1-13
X6
114.285 MHz
20 ppm
2 XA
GND1
GND2 XB
4
GND
REC_CLOCK_C_P
R167
100Ω
REC_CLOCK_C_N
SI5326_INT_ALM
SI5326_RST
See the Silicon Labs Si5324 data sheet for more information on this device

GTX Transceivers

[Figure
The VC707 board provides access to 27 GTX transceivers:
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•
•
•
•
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The GTX transceivers in 7 series FPGAs are grouped into four channels described as
Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below
the GTX Quad of interest. There are four GTX Quads on the VC707 board with connectivity
as shown here:
32
Send Feedback
SI5324_VCC
U24
5
10
32
1
SI5326_XTAL_XA 6
3
SI5326_XTAL_XB 7
C33
0.1μF 25V
X5R
REC_CLOCK_P 16
REC_CLOCK_N 17
NC 12
C34
0.1μF 25V
NC 13
X5R
3
NC 4
NC 11
NC 15
NC 18
19
20
1
21
R16
4.7KΩ 5%
GND
Figure 1-13: Jitter Attenuated Clock
1-2, callout 12]
Eight of the GTX transceivers are wired to the PCI Express x8 endpoint edge
connector (P1) fingers
Eight of the GTX transceivers are wired to the FM1 HPC connector (J35)
Eight of the GTX transceivers are wired to the FMC2 HPC connector (J37)
One GTX is wired to SMA connectors (RX: J27, J28 TX: J29, J30)
One GTX is wired to the SFP/SFP+ Module connector (P3)
One GTX is used for the SGMII connection to the Ethernet PHY (U50)
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Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
NC
VDD1 NC1
9
NC
VDD2 NC2
14
NC
VDD3 NC3
30
NC
XA NC4
33
NC
NC5
29
SI5326_OUT_N
XB CKOUT1_N
28
SI5326_OUT_P
CKOUT1_P
35
NC
CKIN1_P
CKOUT2_P
34
NC
CKOUT2_N
CKIN1_N
CKIN2_P
CKIN2_N
37
GNDPAD
36
INT_C1B CMODE
27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
31
GND3 A1
31
GND4 A2_SS
9
RST_B
GND1
31
CS_CA
GND2
GND
C31
0.1μF 25V
X5R
SI5326_OUT_C_N
SI5326_OUT_C_P
C32
0.1μF 25V
X5R
NC
SI5326_SDA
SI5326_SCL
UG885_c1_13_021412
[Ref 19].
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014