Xilinx VC707 User Manual page 41

Table 1-17: Board Connections for PHY Configuration Pins
Pin Connection on Board
CFG0 V 2.5V
CC
CFG1 Ground
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V
CC
CFG5 PHY_LED_LINK10
CFG6 PHY_LED_RX
The Ethernet connections from FPGA U1 to the 88E1111 PHY device are listed in
Table
Table 1-18: Ethernet Connections, FPGA to PHY Device
FPGA (U1)
AK33
AH31
AL31
AJ33
AN2
AN1
AM8
AM7
VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Bit[2]
Definition and Value
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MD[2] = 1
DIS_FC = 1
SEL_BDT = 0
1-18.
Net Name
Pin
PHY_MDIO
PHY_MDC
PHY_INT
PHY_RESET
SGMII_TX_P
SGMII_TX_N
SGMII_RX_P
SGMII_RX_N
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Bit[1]
Definition and Value
PHYADR[1] = 1 PHYADR[0] = 1
PHYADR[4] = 0 PHYADR[3] = 0
ANEG[2] = 1 ANEG[1] = 1
ENA_XC = 1 DIS_125 = 1
HWCFG_MD[1] = 1 HWCFG_MD[0] = 1
DIS_SLEEP = 1 HWCFG_MD[3] = 1
INT_POL = 1 75/50Ω= 0
M88E1111 PHY U50
Pin Name
M1 MDIO
L3 MDC
L1 INT_B
K3 RESET_B
A3 SIN_P
A4 SIN_N
A7 SOUT_P
A8 SOUT_N
Feature Descriptions
Bit[0]
Definition and Value
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