Linear Bpi Flash Memory - Xilinx VC707 User Manual

Chapter 1: VC707 Evaluation Board Features
Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
The VC707 DDR3 SODIMM interface adheres to the constraints guidelines in the DDR3
Design Guidelines section of 7 Series FPGAs Memory Interface Solutions User Guide (UG586)
[Ref
memory interface details are available in UG586 and 7 Series FPGAs Memory Resources
User Guide (UG473)

Linear BPI Flash Memory

[Figure
The Linear BPI Flash memory located at U3 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI Flash memory device is packaged in a 64-pin BGA.
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The Linear BPI Flash memory can synchronously configure the FPGA in Master BPI mode
at the 80 MHz data rate supported by the PC28F00AG18FE flash memory. The fastest
configuration method uses the external 80 MHz oscillator connected to the FPGA's
EMCCLK pin.
Multiple bitstreams can be stored in the Linear BPI Flash. The two most significant address
bits (A25, A24) of the flash memory are connected to DIP switch SW11 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7VX485T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW11. The
connections between the BPI Flash memory and the FPGA are listed in
Table 1-5: BPI Flash Memory Connections to the FPGA
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FPGA (U1)
Net Name
Pin
K19 DDR3_CKE0
J18 DDR3_CKE1
G18 DDR3_CLK0_N
H19 DDR3_CLK0_P
F19 DDR3_CLK1_N
G19 DDR3_CLK1_P
3]. The VC707 DDR3 SODIMM interface is a 40Ω impedance implementation. Other
[Ref 4].
1-2, callout 3]
Part number: PC28F00AG18FE (Micron)
Supply voltage: 1.8V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 80 MHz
FPGA (U1) Pin Net Name
AJ28 FLASH_A0
AH28 FLASH_A1
AG31 FLASH_A2
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J1 DDR3 Memory
Pin Number Pin Name
73
74
103
101
104
102
BPI Flash Memory (U3)
Pin Number Pin Name
A1 A1
B1 A2
C1 A3
UG885 (v1.4) May 12, 2014
CKE0
CKE1
CK0_N
CK0_P
CK1_N
CK1_P
Table 1-5.
VC707 Evaluation Board