Xilinx VC707 User Manual page 3

Date Version
02/01/13 1.2
08/22/13 1.3
05/12/14 1.4
UG885 (v1.4) May 12, 2014
Updated VC707 Board Features,
FPGA Configuration, USB
2
Video Output, I C Bus, Table
57.1 FMC2 HPC Connector (Partially
Figure 1-25. Updated paragraph following
and Table 1-24. Added CPU Reset
Form Factor Board TI Power System
Replaced PTD08D021W with PTD08D210W in
introduction in Appendix C, Master Constraints File
removed NXP Semiconductors in
paragraph to the introduction in
Updated Figure 1-2, Table
Flash Memory. Replaced Master UCF Listing with
Listing.
Updated disclaimer and copyright. In
to A35, and B37 to A36.
www.xilinx.com
Revision
Table 1-1, Virtex-7 XC7VX485T-2FFG1761C
JTAG, System Clock (SYSCLK_P and
1-15, User I/O, Table 1-26,
Populated). Updated
Table 1-4, Figure
Pushbutton, User Rotary
Cooling. Added
Table
Appendix F, Additional
Appendix G, Regulatory and Compliance
1-1, Table 1-12, Table 1-13, and
Appendix C, Master Constraints File
Table 1-27, changed U1 FPGA pin N39 to M39, B36
FPGA,
SYSCLK_N), HDMI
Power Management, and
Figure 1-5, Figure 1-16, and
1-7, Figure 1-19, Figure
Switch, User SMA, and
Table 1-27 and Table 1-28.
1-29. Added third paragraph to the
Listing. Added UG483 and
Resources. Added second
Information.
Table 1-14. Updated Linear BPI
VC707 Evaluation Board
VITA
1-20,
PCIe