Usb Jtag Interface - Xilinx KCU116 User Manual

The connections between the SD card connector and system controller U161 are listed in
Table 3-4.
Table 3‐4: SD Card Connections to System Controller U161
XC7Z010 Schematic Net
(U161) Name
D6 SDIO_DATA0
C6 SDIO_DATA1
B9 SDIO_DATA2
D10 SDIO_DATA3
B10 DIO_CMD
B7 SDIO_CLK
D8 SDIO_CONN_CD LVCMOS18
For more information on secure digital nonvolatile memory card technology, see the
SanDisk [Ref 24]

USB JTAG Interface

[Figure 2-1, callout 5]
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U21), in which a host computer accesses the KCU116 board JTAG chain
through a type-A (host side) to micro-B (KCU116 board side J2) USB cable.
A 2 mm JTAG header (J8) is also provided in parallel for access by Xilinx
such as the Platform Cable USB II and the Parallel Cable IV. JTAG configuration is allowed at
any time regardless of the FPGA mode pin settings. JTAG initiated configuration takes
priority over the configuration method selected through the FPGA mode pin M2 (which is
wired to DIP SW21 pin 6, switch position 6). The JTAG chain of the KCU116 board is shown
in Figure 3-5. For more details about the Digilent USB JTAG module, see the Digilent
website [Ref 26].
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Level Shifter (U178)
I/O
Standard
Pin Pin
# Name
LVCMOS18 1 IO_VL1
LVCMOS18 3 IO_VL2
LVCMOS18 4 IO_VL3
LVCMOS18 9 IO_VL4
LVCMOS18 10 IO_VL5
LVCMOS18 12 CLK_VL
and SD Association [Ref 25]
www.xilinx.com
Chapter 3: Board Component Descriptions
Schematic Net Name
Pin
Pin Name
#
IO_VCC1 15 SDIO_CONN_DATA0
IO_VCC2 5 SDIO_CONN_DATA1
IO_VCC3 6 SDIO_CONN_DATA2
IOVCC4 7 SDIO_CONN_DATA3
IO_VCC5 8 SDIO_CONN_CMD
CLK_VCC 14 SDIO_CONN_CLK
Direct Connect
websites.
SDIO
Connector
(J177)
Pin
Pin Name
#
7 DAT0
8 DAT1
1 DAT2
2 CD_DAT3
3 CMD
5 CLK
13 DETECT
®
download cables,
26
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