Usb Jtag Module - Xilinx AC701 User Manual

Table 1-7
Table 1-7: SDIO Connections to the FPGA

USB JTAG Module

[Figure
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U26) where a host computer accesses the AC701 board JTAG chain through
a standard-A plug (host side) to micro-B plug (AC701 board side) USB cable.
A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables
such as the Platform Cable USB II and the Parallel Cable IV.
The JTAG chain of the AC701 board is illustrated in
allowed at any time regardless of FPGA mode pin settings. JTAG initiated configuration
takes priority over the configuration method selected through the FPGA mode pin settings
at SW1.
X-Ref Target - Figure 1-8
USB
Module
(U26)
or
JTAG
Connector
(J4)
TDO
TDI
AC701 Evaluation Board
UG952 (v1.2) August 28, 2013
lists the SD card interface connections to the FPGA.
U1 FPGA Pin
Schematic Net Name
Name
R20
P24
N23
N24
P23
N19
P19
P21 SDIO_CD_DAT3
1-2, callout 5]
SPST Bus Switch
U27
J30
FMC HPC
Connector
Part of U19
BUFFER
TDI TDO
Figure 1-8: JTAG Chain Block Diagram
www.xilinx.com
Pin Number
SDIO_SDWP
SDIO_SDDET
SDIO_CMD
SDIO_CLK
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0
Figure
N.C.
Part of U19
BUFFER
Feature Descriptions
U29 SDIO Connector
Pin Name
11 SDWP
10 SDDET
2 CMD
5 CLK
9 DAT2
8 DAT1
7 DAT0
1 CD_DAT3
1-8. JTAG configuration is
U1
FPGA
TDI
TDO
UG952_c1_08_012913
19