Usb Jtag - Xilinx ML605 Hardware User's Manual

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where
a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to
Type-Mini-B (ML605 side) USB cable.
The JTAG chain of the board is illustrated in the figure below. JTAG configuration is
allowable at any time under any mode pin setting. JTAG initiated configuration takes
priority over the mode pin settings.
X-Ref Target - Figure 1-4
J22
FMC bypass jumpers J17 and J18 must be connected between pins 1-2 (bypass) to enable
JTAG access to the FPGA on the basic ML605 board (without FMC expansion modules
installed), as shown in
expansion connectors are populated with an expansion module that has a JTAG chain, the
respective jumper(s) must be set to connect pins 2-3 in order to include the FMC expansion
module's JTAG chain in the main ML605 JTAG chain.
X-Ref Target - Figure 1-5
X-Ref Target - Figure 1-6
ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
J17
FMC HPC
TDI TDO TDI
J64
Figure 1-4: JTAG Chain Diagram
Figure 1-5
FMC_TDI_BUF
FMC_LPC_TDI
FMC_HPC_TDO
Figure 1-5: VITA 57.1 FMC HPC (J64) JTAG Bypass Jumper J17
FMC_LPC_TDI
SYSACE_TDI
FMC_LPC_TDO
Figure 1-6: VITA 57.1 FMC LPC (J63) JTAG Bypass Jumper J18
www.xilinx.com
J18
3.3V
FMC LPC System ACE CF
TDO
TSTTDI
J63
TSTTDO
and Figure 1-6. When either or both VITA 57.1 FMC
J17
1
Bypass FMC HPC J64 = Jumper 1-2
2
Include FMC HPC J64 = Jumper 2-3
3
H - 1x3
J18
1
Bypass FMC LPC J63 = Jumper 1-2
2
Include FMC LPC J63 = Jumper 2-3
3
H - 1x3
Detailed Description
2.5V
FPGA
TDI
CFGTDO
U1
U19
CFGTDI TDO
UG534_04_081309
UG534_05_081309
UG534_06_081309
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