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(3) Priority specification flag registers (PR0L, PR0H)
The priority specification flag is used to set the corresponding maskable interrupt priority order.
PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used
as a 16-bit register PR0, use a 16-bit memory manipulation instruction for setting.
RESET input sets these registers to FFH.
Figure 16-4. Format of Priority Specification Flag Register
Symbol
<7>
<6>
<5>
PR0L
TMPR3
CSIPR1
CSIPR0
7
6
5
PR0H
1
1
1
Cautions 1. When the watchdog timer is used in watchdog timer mode 1, set the TMPR4 flag to 1.
2. Always set bits 5 to 7 of PR0H to 1.
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CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
<4>
<3>
<2>
<1>
PPR3
PPR2 PPR1
PPR0
<4>
<3>
<2>
<1>
KSPR
ADPR
TMPR2
TMPR1
User's Manual U11302EJ4V0UM
<0>
Address
After reset
FFE8H
FFH
TMPR4
<0>
TMPR0
FFE9H
FFH
xxPR
Priority level selection
High priority level
0
Low priority level
1
R/W
R/W
R/W
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