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Figure 1-23
X-Ref Target - Figure 1-23
VITA 57.1 FMC1 HPC Connector (Partially Populated)
[Figure
The VC709 board implements one instance of the FMC HPC VITA 57.1 specification
connector. This section discusses the FMC1 HPC J35 connector.
Note:
away from the VC709 board.
The VITA 57.1 FMC standard calls a high pin count (HPC), 400 pin 10 x 40 position form
factor connector. The 10 x 40 rows of an FMC HPC connector provides pins for up to:
•
•
•
•
•
The VC709 board FMC1 HPC connector J35 implements a subset of the maximum signal
and clock connectivity capabilities:
•
•
•
•
The FMC1 HPC signals are distributed across GTH Quads 117, 118, and 119.
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
shows the SW11 circuit.
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
R341
1.21kΩ
0.1 W
1%
R340
1.21kΩ
0.1 W
1%
GND
Figure 1-23: Configuration Mode and Upper Linear Flash Address Switch
1-2, callout 22]
The FMC1 HPC J35 connector is a keyed connector oriented so that a plug-on card faces
160 single-ended or 80 differential user-defined signals
10 GTH transceivers
2 GTH clocks
4 differential clocks
159 ground and 15 power connections
80 differential user-defined pairs:
•
34 LA pairs (LA00-LA33)
•
24 HA pairs (HA00-HA23)
•
22 HB pairs (HB00-HB21)
10 GTH transceivers
2 GTH clocks
2 differential clocks
www.xilinx.com
VCC1V8
SW11
1
10
9
2
3
8
7
4
5
6
SDA05H1SBD
R339
R337
1.21kΩ
1.21kΩ
0.1 W
0.1 W
1%
1%
R338
1.21kΩ
0.1 W
1%
Feature Descriptions
R226
R227
220Ω
220Ω
0.1 W
0.1 W
1%
1%
UG887_c1_23_090612
49
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