Real-Time Interrupt (Rti) Timer With Digital Watchdog - Texas Instruments TMS320C6722 User Manual

Floating-point digital signal processors
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4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog

4.16.1 RTI/Digital Watchdog Device-Specific Information
C672x includes an RTI timer module which is used to generate periodic interrupts. This module also
includes an optional digital watchdog feature.
SYSCLK2
32-Bit + 32-Bit Prescale
(Used by DSP BIOS)
32-Bit + 32-Bit Prescale
32-Bit + 32-Bit Prescale
32-Bit + 32-Bit Prescale
The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 (but
may be started individually and may have different prescaler settings).
The counters provide the timebase against which four output comparators operate. These comparators
may be programmed to generate periodic interrupts. The comparators include an adder which
automatically updates the compare value after each periodic interrupt. This means that the DSP only
needs to initialize the comparator once with the interrupt period.
The two input captures can be triggered from any of the McASP0, McASP1, or McASP2 DMA events. The
device configuration register which selects the McASP events to measure is defined in
Measuring the time difference between these events provides an accurate measure of the sample rates at
which the McASPs are transmitting and receiving. This measurement can be useful as a hardware assist
for a software asynchronous sample rate converter algorithm.
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Counter 0
Capture 0
Counter 1
Capture 1
Controlled by
CFGRTI Register
McASP0,1,2
Transmit/Receive
DMA Events
McASP0,1,2
Transmit/Receive
DMA Events
Figure 4-40. RTI Timer Block Diagram
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Figure 4-40
contains a block diagram of the RTI module.
Compare 0
32-Bit
Compare 1
32-Bit
Compare 2
32-Bit
Compare 3
32-Bit
Digital Watchdog
25-Bit Counter
Watchdog Key Register
16-Bit Key
Peripheral and Electrical Specifications
SPRS268E – MAY 2005 – REVISED JANUARY 2007
RTI Interrupt 0
RTI Interrupt 1
RTI Interrupt 2
RTI Interrupt 3
RESET
(Internal Only)
Table
4-37.
97

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