Erren1 - Error Detection Enable 1 - IBM CPC700 User Manual

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3.16.3 ERREN1 - Error Detection Enable 1

Address Offset: x08
Width: 32
Reset Value: x0800_0000
Access: Read/Write
The following register is used to enable the detection and corresponding reporting mechanism for the as-
sociated error.
Bit Name
0 C_TT_ER_EN
1 M_SEL_ER_EN
2 PLB_M_ER_EN
3 PLBM_LEN
4 PLB_S_ER_EN
CPC700 User's Manual—Preliminary
0 60x Data Parity Error
0 - No Error Detected
1 - Error Detected
0s Reserved
Reset Description
Value
0 CPU Transfer Type Error Enable
0 - Detection Disabled
1 - Detection Enabled
0 Memory Select Error Enable
0 - Detection Disabled
1 - Detection Enabled
0 PLB Master Error Detection Enable
0 - Detection Disabled
1 - Detection Enabled
This bit enables the detection of PLB Slave errors associated
with transfers initiated by the 60x PLB Master.
Errors are asserted by a slave via the Merr signal.
0 PLB Master Lock Error Enable
0 - Disable PLB Master LockErr Signal Assertion
1 - Enable PLB Master LockErr Signal Assertion
This bit enables the assertion of the 60x PLB master's
M_lockErr signal, telling the slave to trap and hold error status
information when an error occurs. The M_lockErr signal re-
mains asserted as long as this bit is enabled.
1 PLB Slave Error Generation Enable
0 - Detection Disabled
1 - Detection Enabled
This bit enables the detection of memory select errors associ-
ated with a PLB Master access to system memory.
It enables the assertion of Merr by a PLB slave, and the trap-
ping of address information in the BESR and BEAR registers.
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