Chapter 9. General Purpose Timers; Introduction; Gpt Registers; Table 96. Gpt Registers - IBM CPC700 User Manual

Chapter 9. General Purpose Timers

9.1 Introduction

The General Purpose Timer (GPT) provides a separate time base counter and system timers for the
CPC700. Five capture timers and five compare timers are implemented in the GPT macro. The following
sections include a list of major features, an overview, supported configurability, and register descriptions of
the General Purpose Timer core.
Features of the General Purpose Timer core include:
• 32 bit time base
- Time base counter is updated once every CPC700 SYS_CLOCK
• Memory mapped registers provide direct control of all GPT functions
• Five capture event timers and five compare timers
- Each capable of interrupting the processor when properly enabled

9.1.1 GPT Registers

All GPT registers are memory mapped and accessed via load/store instructions using the addresses
shown in Table 96.
Base Address Register
FF65_0000 GPTTBC
FF65_0004 GPTCE
FF65_0008 GPTEC
FF65_000C GPTSC
FF65_0010
FF65_0014
FF65_0018 GPTIM
FF65_001C GPTISS
FF65_0020 GPTISC
FF65_0024 GPTIE
FF65_0028 -
FF65_003C
FF65_0040 GPTCAPT0
FF65_0044 GPTCAPT1
FF65_0048 GPTCAPT2
FF65_004C GPTCAPT3
FF65_0050 GPTCAPT4
FF65_0054 -
FF65_007C
FF65_0080 GPTCOMP0
FF65_0084 GPTCOMP1
CPC700 User's Manual—Preliminary

Table 96. GPT Registers

Register Name
GPT Time Base Counter
GPT Capture Enable
GPT Edge-Detection Control
GPT Synchronization Control
(Reserved)
(Reserved)
GPT Interrupt Mask
GPT Interrupt Status (Set bits if write 1)
GPT Interrupt Status (Clear bits if write 1)
GPT Interrupt Enable
(Reserved)
GPT Capture Timer 0
GPT Capture Timer 1
GPT Capture Timer 2
GPT Capture Timer 3
GPT Capture Timer 4
(Reserved)
GPT Compare Timer 0
GPT Compare Timer 1
Access Width
Mode (bits)
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
R/W 32
Read 32
Read 32
Read 32
Read 32
Read 32
R/W 32
R/W 32
9-1