Chapter 4. Memory Controller; Features - IBM CPC700 User Manual

Chapter 4. Memory Controller

The Memory Controller provides the local PowerPC processor with a low latency access path to
CPC700
local memory and external peripherals. In addition it supports hardware coherent accesses to the proces-
sor's local memory from the PCI bus. Coherency is maintained on PCI accesses to local memory by
snooping the processor's L1 cache before allowing the PCI interface to complete the requested access.
Industry standard 72-pin and 168-pin modules are supported allowing for a variety of system memory con-
figurations. The memory controller supports up to 5 banks (5 Chip Select outputs). Bank 0 is dedicated to
Boot ROM while banks 1-4 may be programmed to support either SDRAM, ROM, SRAM, or external
peripherals. A maximum of 512MBytes per bank is supported with an overall maximum of 2GB for all
banks combined. Memory timings, bank starting and ending addresses, and memory addressing mode are
all programmable. During reset, Bank 0 defaults to ROM and is enabled while all other banks are disabled.
Bank 0 is typically used for the boot ROM.

4.1 Features

Synchronous DRAM:
• Memory bus operates at the same frequency as the processor bus (up to 66 MHz with CPC700-66 or
up to 83 MHz with CPC700-83)
• Up to 4 banks (Bank 0 defaults to ROM)
• 11x9 to 13x11 addressing for SDRAM (2 or 4 internal banks)
• 8 MByte to 512 MByte per bank
• Programmable timings and address mapping
• CAS before RAS refresh w/programmable refresh timer
• Supports hardware coherency
• Page Mode Accesses
• Sync DRAM configuration via mode set command
• 64-bit and 32-bit memory interface options (72-bit or 40-bit if implementing ECC)
• SDRAM Self-Refresh mode support (bank 4 only)
ROM/Peripheral:
• ROM, EPROM, SRAM, and Peripherals supported
• Burst and Non-Burst devices
• 1-5 banks (shared with SDRAM)
• 8, 16, 32, and 64-bit data bus widths supported
• Programmable timing per bank
• Shared address/data/control with DRAM interface
• External latch control for shared address bus support
CPC700 User's Manual—Preliminary 4-1